View ACPL-796J-560E_7061866.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

acpl-796j optically isolated sigma-delta modulator data sheet caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. description the acpl-796j is a 1-bit, second-order sigma-delta ( ) modulator converts an analog input signal into a high- speed data stream with galvanic isolation based on optical coupling technology. the acpl-796j operates from a 5 v power supply with dynamic range of 80 db with an appro- priate digital filter. the differential inputs of 200 mv (full scale 320 mv) are ideal for direct connection to shunt resistors or other low-level signal sources in applications such as motor phase current measurement. the analog input is continuously sampled by means of sigma-delta over-sampling using external clock, coupled across the isolation barrier, which allows synchronous operation with any digital controller. the signal infor- mation is contained in the modulator data, as a density of ones with data rate up to 20 mhz, and the data are encoded and transmitted across the isolation boundary where they are recovered and decoded into high-speed data stream of digital ones and zeros. the original signal information can be reconstructed with a digital filter. the serial interface has a wide supply range of 3 v to 5.5 v. combined with superior optical coupling technology, the modulator delivers high noise margins and excellent immunity against isolation-mode transients. with 0.5 mm minimum distance through insulation (dti), the acpl-796j provides reliable double protection and high working insulation voltage, which is suitable for fail-safe designs. this outstanding isolation performance is superior to alternatives including devices based on capacitive- or magnetic-coupling with dti in micro-meter range. offered in an so-16 package, the isolated adc delivers the reli- ability, small size, superior isolation and over-temperature performance motor drive designers need to accurately measure current at much lower price compared to tradi- tional current transducers. the internal clock version modulators, hcpl-7860 (dip-8/ gull wing surface mount package) and hcpl-786j (so-16 package), are also available. features 5 mhz to 20 mhz external clock input range 1-bit, second-order sigma-delta modulator 16 bits resolution no missing codes (12 bits enob) 74 db minimum snr 3.5 v/c maximum offset drift 1% maximum gain error internal reference voltage 200 mv linear range with single 5 v supply 3 v to 5.5 v wide supply range for digital interface C40c to +105c operating temperature range so-16 package 25 kv/ s common-mode transient immunity safety and regulatory approval (pending): iec/en/din en 60747-5-5: 1230 vpeak working insulation voltage ul 1577: 5000 vrms/1min double protection rating csa: component acceptance notice #5 applications motor phase and rail current sensing power inverter current and voltage sensing industrial process control data acquisition systems general purpose current and voltage sensing traditional current transducer replacements functional block diagram figure 1. ? mo d u la tor/ en c o d er v in s hie ld v in b uf v ref l e d d river cl o c k d ete c tor s hie ld d e c o d er l e d d river m cl kin m da t v dd 2 gn d 2 gn d 1 v dd 1 acpl - 796j + ?
2 pin configuration and descriptions v dd1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v in + v in C gnd1 nc nc v dd1 gnd1 gnd2 nc v dd2 mclkin nc mdat nc gnd2 acpl-796j figure 2 . pin configuration. table 1. pin descriptions. pin n o. symbol description 1, 7 v dd1 supply voltage for signal input side (analog side), relative to gnd1 2v in + positive analog input, recommended input range 200 mv 3v in C negative analog input, recommended input range 200 mv (normally connected to gnd1) 4, 8 gnd1 supply ground for signal input side 5, 6, 10, 12, 15 nc no connection. leave floating 9, 16 gnd2 supply ground for data output side (digital side) 11 mdat modulator data output 13 mclkin modulator clock input, 5 mhz to 20 mhz 14 v dd2 supply voltage for data output side, relative to gnd2 table 2 . o rdering information acpl-796j is ul recognized with 5000 vrms/1 minute rating per ul 1577 (pending). part number o ption ( r ohs compliant) package surface m ount tape& r eel i e c /en/ di n en 60747-5-5 quantity acpl-796j -000e so-16 x 45 per tube -060e x x 45 per tube -500e x x 850 per reel -560e x x x 850 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example: ACPL-796J-560E to order product of surface mount package in tape and reel packaging with iec/en/din en 60747-5-5 safety approval and rohs compliance. option datasheets are available. contact your avago sales representative or authorized distributor for information.
3 package o utline drawings 16-lead surface m ount (s o -16) 9 7.493 0.254 (0.295 0.010) 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 0.457 (0.018) 3.505 0.127 (0.138 0.005) 9 10.312 0.254 (0.406 0.10) 10.160 0.254 (0.408 0.010) 0.025 min. 0.203 0.076 (0.008 0.003) standoff 8.986 0.254 (0.345 0.010) 0-8 0.457 (0.018) 1.270 (0.050) all leads to be coplanar 0.002 a 796j yyww type number date code 11.63 (0.458) 2.16 (0.085) 0.64 (0.025) land pattern recommendation dimensions in millimeters and (inches). note: floating lead protrusion is 0.15 mm (6 mils) max. note: initial and continued variation in color of the white mold compound is normal and does not affect performance or reliability of the device. figure 3. 16-lead surface m ount. r ecommended pb-free i r profile recommended reflow condition as per jedec standard, j-std-020 (latest revision). non-halide flux should be used. r egulatory information the acpl-796j is pending for approvals by the following organizations: csa approval under csa component acceptance notice #5, file ca 88324. i e c /en/ di n en 60747-5-5 approved with maximum working insulation voltage v iorm = 1230 vpeak. u l approval under ul 1577, component recognition program up to v iso = 5000 vrms/1min. file e55361.
4 table 3. i e c /en/ di n en 60747-5-5 insulation characteristics [1] description symbol v alue u nits installation classification per din vde 0110/1.89, table 1 for rated mains voltage 150 vrms for rated mains voltage 300 vrms for rated mains voltage 450 v rms for rated mains voltage 600 vrms for rated mains voltage 1000 vrms i-iv i-iv i-iv i-iv i-iii climatic classification 55/105/21 pollution degree (din vde 0110/1.89) 2 maximum working insulation voltage v iorm 1230 vpeak input to output test voltage, method b v iorm 1.875 = v pr , 100% production test with t m = 1 sec, partial discharge < 5 pc v pr 2306 vpeak input to output test voltage, method a v iorm 1.6 = v pr , type and sample test, t m = 10 sec, partial discharge < 5 pc v pr 1968 vpeak highest allowable overvoltage (transient overvoltage, t ini = 60 sec) v iotm 8000 vpeak safety-limiting values (maximum values allowed in the event of a failure) case temperature input current [2] output power [2] t s i s,input p s,output 175 400 600 c ma mw insulation resistance at t s , v io = 500 v r s 10 9 output power - p s , input current - i s 0 0 t s - case temperature - o c 200 50 400 125 25 75 100 150 600 800 200 100 300 500 700 175 p s (mw) i s (ma) figure 4. notes: 1. insulation characteristics are guaranteed only within the safety maximum ratings, which must be ensured by protective circuits within the application. 2. safety-limiting parameters are dependen t on ambient temperature. refer to the following figure for dependence of p s and i s on ambient temperature.
5 table 5. absolute m aximum r atings parameter symbol m in. m ax. u nits storage temperature t s C55 +125 c ambient operating temperature t a C40 +105 c supply voltage v dd1 , v dd2 C0.5 6.0 v steady-state input voltage [1,3] v in +, v in CC2v dd1 + 0.5 v two-second transient input voltage [2] v in +, v in CC6v dd1 + 0.5 v digital input/output voltages mclkin, mdat C0.5 v dd2 + 0.5 v lead solder temperature 260c for 10 sec., 1.6 mm below seating plane notes: 1. dc voltage of up to C2 v on the inputs does not cause latch-up or damage to the device; tested at typical operating conditio ns. 2. transient voltage of 2 seconds up to C6 v on the inputs does not cause latch-up or damage to the device; tested at typical o perating conditions. 3. absolute maximum dc current on the inputs = 100 ma, no latch-up or device damage occurs. table 6. r ecommended o perating conditions parameter symbol m in. m ax. u nits ambient operating temperature t a C40 +105 c v dd1 supply voltage v dd1 4.5 5.5 v v dd2 supply voltage v dd2 3 5.5 v analog input voltage [1] v in +, v in C C200 +200 mv notes: 1. full scale signal input range 320 mv. table 4. insulation and safety r elated specifications parameter symbol v alue u nits conditions minimum external air gap (external clearance) l(101) 8.3 mm measured from input terminals to output terminals, shortest distance through air minimum external tracking (external creepage) l(102) 8.3 mm measured from input terminals to output terminals, shortest distance path along body minimum internal plastic gap (internal clearance) 0.5 mm through insulation distance, conductor to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity tracking resistance (comparative tracking index) cti >175 v din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0110, 1/89, table 1)
6 table 7. e lectrical specifications unless otherwise noted, t a = C40c to +105c, v dd1 = 4.5 v to 5.5 v, v dd2 = 3 v to 5.5 v, v in + = C200 mv to +200 mv, and v in C = 0 v (single-ended connection); tested with sinc 3 filter, 256 decimation ratio, f mclkin = 10 mhz. parameter symbol m in. typ. [1] m ax. u nits test conditions /n otes fig. static cha r act er istics resolution 16 bits decimation filter output set to 16 bits integral nonlinearity inl C15 3 15 lsb t a = C40c to +85c; see definitions section C25 3 25 lsb t a = 85c to 105c C25 25 v in + = C250 mv to +250mv differential nonlinearity dnl C0.9 0.9 lsb no missing codes, guaranteed by design; see definitions section offset error v os C1 3 4.5 mv t a = C40c to +105c; see definitions section offset drift vs. temperature tcv os 3.5 v/c offset drift vs. v dd1 120 v/v gain error g e C2 2 % t a = C40c to +105c, v in + = C250 to +250 mv; see definitions section C1 1 % t a = 25c, v in + = C250 to +250 mv gain error drift vs. temperature tcg e 60 ppm/c gain error drift vs. v dd1 110 v/v a n al og i n p u ts full-scale differential voltage input range fsr 320 mv v in = v in + C v in C; note 2 average input bias current i ina C0.5 a v dd1 = 5v, v dd2 = 5v, v in + = 0 v; note 3 6 average input resistance r in 33 k across v in + or v in C to gnd1; note 3 input capacitance c ina 8 pf across v in + or v in C to gnd1 dy n a m ic cha r act er istics v in + = C200 mv to +200 mv, 543 hz, sine wave; note 4 signal-to-noise ratio snr 74 80 db t a = C40c to +105c; see definitions section signal-to- (noise + distortion) ratio sndr 65 75 db t a = C40c to +105c; see definitions section 7, 8 68 75 db t a = C40c to +85c 7, 8 65 t a = C40c to +105c, v in + = C250 mv to +250 mv 7 effective number of bits enob 12 bits see definitions section isolation transient immunity cmr 25 kv/ v v cm = 1 kv; see definitions section common-mode rejection ratio cmrr 74 db di g ital i n p u ts a n d ou tp u ts input high voltage v ih 0.8 v dd2 v note 5 input low voltage v il 0.2 v dd2 v note 5 input current i ind 0.5 a input capacitance c ind 6pf output high voltage v oh v dd2 C 0.2 v dd2 C 0.1 v v dd2 = 5 v supply, i out = C200 a v dd2 C 0.15 v dd2 C 0.1 v v dd2 = 3.3 v supply, i out = C200 a output low voltage v ol 0.4 v i out = +200 a p o w er s u pply v dd1 supply current i dd1 14 19 ma 9, 10 v dd2 supply current i dd2 68mav dd2 = 5 v supply 11, 12 57mav dd2 = 3.3 v supply notes: 1. all typical values are at t a = 25c, v dd1 = 5 v, v dd2 = 5 v. 2. beyond the full-scale input range the data output is either all zeroes or all ones. 3. because of the switched-capacitor nature of the isolated modulator, time averaged values are shown. 4. signal frequency of 543 hz is used as a reference frequency for coherent sampling. 5. ensured by design.
7 table 8. timing specifications unless otherwise noted, t a = C40c to +105c, v dd1 = 4.5 v to 5.5 v, v dd2 = 3 v to 5.5 v. parameter symbol m in. typ. m ax. u nits test conditions /n otes fig. modulator clock input frequency f mclkin 5 10 20 mhz clock duty cycle 40% to 60% data delay after rising edge of mclkin [1] t d 315nsc l = 15 pf 5 notes: 1. data changes at the clock rising edge so it can be safely read at the falling edge, although it can be read at the rising ed ge if preferred. figure 5. data timing. t d mclkin mdat table 9. package characteristics parameter symbol m in. typ. m ax. u nits test conditions n ote input-output momentary withstand voltage v iso 5000 vrms rh 50%, t = 1 min; t a = 25c 1, 2 input-output resistance r i-o 10 12 10 13 v i-o = 500 vdc 2 10 11 t a = 100c 2 input-output capacitance c i-o 1.4 pf f = 1 mhz 2 input ic junction-to-ambient thermal resistance jai 83 c/w 1 oz. trace, 2-layer pcb, still air, t a = 25c 3 output ic junction-to- ambient thermal resistance jao 85 c/w 1 oz. trace, 2-layer pcb, still air, t a = 25c 3 notes: 1. in accordance with ul 1577, each optocoupler is proof tested by applying an insulation test voltage 6000 vrms for 1 second . this test is performed before the 100% production test for partial discharge (method b) shown in iec/en/din en 60747-5-5 insulation characteristic tab le. 2. this is a two-terminal measurement: pins 1-8 are shorted together and pins 9-16 are shorted together. 3. maximum power dissipation in analog side and digital side ics needs to be limited to ensure that their respective junction temperature is less than 125c. the maximum permissible power dissipation is dependent on the thermal impedance and the ambient temperature.
8 typical performance plots unless otherwise noted, t a = 25c, v dd1 = 5 v, v dd2 = 5 v, v in + = C200 mv to +200 mv, and v in C = 0 v, f mclkin = 10 mhz, with sinc 3 filter, 256 decimation ratio. -50 -40 -30 -20 -10 0 10 20 30 40 50 -400 -320 -240 -160 -80 0 80 160 240 320 400 v in + (mv) i in + ( a) 60 62 64 66 68 70 72 74 76 78 80 50 75 100 125 150 175 200 225 250 275 300 v in + (mv) sndr (db) 70 71 72 73 74 75 76 77 78 79 80 -40 -20 0 20 40 60 80 100 120 temperature (c) sndr (db) 6 8 10 12 14 16 18 20 -320 -240 -160 -80 0 80 160 240 320 v in + (mv) i dd1 (ma) 6 8 10 12 14 16 18 20 -320 -240 -160 -80 0 80 160 240 320 v in + (mv) i dd1 (ma) mclkin = 20 mhz mclkin = 10 mhz mclkin = 5 mhz mclkin = 10 mhz mclkin = 20 mhz mclkin = 5 mhz f in = 543 hz mclkin = 20 mhz mclkin = 10 mhz mclkin = 5 mhz f in = 543 hz t a = +105c t a = +85c t a = C40c t a = +25c mclkin = 20 mhz mclkin = 10 mhz mclkin = 5 mhz figure 6. input current vs. input voltage. figure 7. s n d r vs. input voltage v i n . figure 8. s n d r vs. temperature. figure 9. i dd1 vs. v i n dc input at various temperatures. figure 10. i dd1 vs. v i n dc input for various frequencies.
9 figure 11. i dd 2 vs. v i n dc input at various temperatures. figure 1 2 . i dd 2 vs. v i n dc input for various frequencies. 2 3 4 5 6 7 8 -320 -240 -160 -80 0 80 160 240 320 v in + (mv) i dd2 (ma) 2 3 4 5 6 7 8 -320 -240 -160 -80 0 80 160 240 320 v in + (mv) i dd2 (ma) t a = +105c t a = +85c t a = C40c t a = +25c mclkin = 20 mhz mclkin = 10 mhz mclkin = 5 mhz definitions integral n onlinearity (i n l) inl is the maximum deviation of a transfer curve from a straight line passing through the endpoints of the adc transfer function, with offset and gain errors adjusted out. differential n onlinearity (d n l) dnl is the deviation of an actual code width from the ideal value of 1 lsb between any two adjacent codes in the adc transfer curve. dnl is a critical specification in closed-loop applications. a dnl error of less than 1 lsb guarantees no missing codes and a monotonic transfer function. o ffset e rror offset error is the deviation of the actual input voltage corresponding to the mid-scale code (32,768 for a 16-bit system with an unsigned decimation filter) from 0 v. offset error can be corrected by software or hardware. g ain e rror gain error is the the difference between the ideal gain slope and the actual gain slope, with offset error adjusted out. gain error includes reference error. gain error can be corrected by software or hardware. signal-to- n oise r atio (s nr ) the snr is the measured ratio of ac signal power to noise power below half of the sampling frequency. the noise power excludes harmonic signals and dc. signal-to-( n oise + distortion) r atio (s n d r ) the sndr is the measured ratio of ac signal power to noise plus distortion power at the output of the adc. the signal power is the rms amplitude of the fundamental input signal. noise plus distortion power is the rms sum of all non-fundamental signals up to half the sampling frequency (excluding dc). e ffective n umber of bits ( eno b) the enob determines the effective resolution of an adc, expressed in bits, defined by enob = (sndr ? 1.76)/6.02 isolation transient immunity (c mr ) the isolation transient immunity (also known as common- mode rejection or cmr) specifies the minimum rate-of- rise/fall of a common-mode signal applied across the isolation boundary beyond which the modulator clock or data is corrupted.
10 product o verview description the acpl-796j isolated sigma-delta ( ) modulator converts an analog input signal into a high-speed (up to 20 mhz) single-bit data stream by means of a sigma- delta over-sampling modulator. the time average of the modulator data is directly proportional to the input signal voltage. the modulator uses external clock ranges from 5 mhz to 20 mhz that is coupled across the isolation barrier. this arrangement allows synchronous operation of data acquisition to any digital controller, and adjustable clock for speed requirements of the application. the modulator data are encoded and transmitted across the isolation boundary where they are recovered and decoded into high-speed data stream of digital ones and zeros. the original signal information is represented by the density of ones in the data output. the other main function of the modulator (optocoupler) is to provide galvanic isolation between the analog signal input and the digital data output. it provides high noise margins and excellent immunity against isolation-mode transients that allows direct measurement of low-level signals in highly noisy environments, for example mea- surement of moor phase currents in power inverters. with 0.5 mm minimum dti, the acpl-796j provides reliable double protection and high working insulation voltage, which is suitable for fail-safe designs. this outstanding isolation performance is superior to alternatives including devices based on capacitive- or magnetic-coupling with dti in micro-meter range. offered in an so-16 package, the isolated adc delivers the reliability, small size, superior isolation and over-temperature performance motor drive designers need to accurately measure current at much lower price compared to traditional current transducers. analog input the differential analog inputs of the acpl-796j are im- plemented with a fully-differential, switched-capacitor circuit. the acpl-796j accepts signal of 200 mv (full scale 320 mv), which is ideal for direct connection to shunt based current sensing or other low-level signal sources applications such as motor phase current measurement. an internal voltage reference determines the full-scale analog input range of the modulator (320 mv); an input range of 200 mv is recommended to achieve optimal performance. users are able to use higher input range, for example 250 mv, as long as within full-scale range, for purpose of over-current or overload detection. figure 13 shows the simplified equivalent circuit of the analog input. figure 13. analog input equivalent circuit. in the typical application circuit (figure 18), the acpl-796j is connected in a single-ended input mode. given the fully differential input structure, a differential input con- nection method (balanced input mode as shown in figure 14) is recommended to achieve better performance. the input currents created by the switching actions on both of the pins are balanced on the filter resistors and cancelled out each other. any noise induced on one pin will be coupled to the other pin by the capacitor c and creates only common mode noise which is rejected by the device. typical value for ra and rb is 22 and 10 nf for c. figure 14. simplified differential input connection diagram. 200 (typ) 3 pf (typ) 3 pf (typ) f switch = mclkin v in + v in C 200 (typ) 1.5 pf 1.5 pf common mode voltage f switch = mclkin analog ground v in + v in C acpl-796j v dd1 gnd1 5 v +analog input C ra rb c Canalog input
11 latch-up consideration latch-up risk of cmos devices needs careful consider- ation, especially in applications with direct connection to signal source that is subject to frequent transient noise. the analog input structure of the acpl-796j is designed to be resilient to transients and surges, which are often encountered in highly noisy application environments such as motor drive and other power inverter systems. other situations could cause transient voltages to the inputs include short circuit and overload conditions. the acpl-796j is tested with dc voltage of up to C2 v and 2- second transient voltage of up to C6 v to the analog inputs and there is no latch-up or damage to the device. figure 15. m oudlator output vs. analog input. m odulator data o utput input signal information is contained in the modulator output data stream, represented by the density of ones and zeros. the density of ones is proportional to the input signal voltage, as shown in figure 15. a differential input signal of 0 v ideally produces a data stream of ones 50% of the time and zeros 50% of the time. a differential input of C200 mv corresponds to 18.75% density of ones, and a differential input of +200 mv is represented by 81.25% density of ones in the data stream. a differential input of +320 mv or higher results in ideally all ones in the data stream, while input of C320 mv or lower will result in all zeros ideally. table 10 shows this relationship. Cfs (analog input) +fs (analog input) 0 v (analog input) time modulator output analog input table 10. input voltage with ideal corresponding density of 1s at modulator data output, and adc code. analog input v oltage input density of 1s adc code (16-bit unsigned decimation) full-scale range 640 mv +full-scale +320 mv 100% 65,535 +recommended input range +200 mv 81.25% 53,248 zero 0 mv 50% 32,768 Crecommended input range C200 mv 18.75% 12,288 Cfull-scale C320 mv 0% 0 notes: 1. with bipolar offset binary coding scheme, the digital code begins with digital 0 at Cfs input and increases proportionally to the analog input until the full-scale code is reached at the +fs input. the zero crossing occurs at the mid-scale input. 2. ideal density of 1s at modulator data output can be calculated with v in /640 mv + 50%; similarly, the adc code can be calculated with (v in /640 mv) 65,536 + 32,768, assuming a 16-bit unsigned decimation filter.
12 digital filter a digital filter converts the single-bit data stream from the modulator into a multi-bit output word similar to the digital output of a conventional a/d converter. with this conversion, the data rate of the word output is also reduced (decimation). a sinc 3 filter is recommended to work together with the acpl-796j. with a 10 mhz external note: in applications, a 0.1 f bypass capacitor must be connected between pins v dd1 and gnd1, and between pins v dd2 and gnd2 of the acpl-796j. figure 16. typical application circuit with a sinc 3 filter. digital interface ic the hcpl-0872 digital interface ic (so-16 package) is a digital filter that converts the single-bit data stream from the modulator into 15-bit output words and provides a serial output interface that is compatible with spi?, qspi?, and microwire? protocols, allowing direct connection to a figure 17. typical application circuit with the hcpl-087 2 . available in an so-16 surface-mount package, the digital interface ic has features include five different conver- sion modes (combinations of speed and resolution), three different pre-trigger modes (allows conversion time <1 s), offset calibration, fast over-range (over-current, or short circuits) detection, and adjustable threshold detection. programmable features are configured via the acpl-796j 3-wire serial interface input current r shunt v in + v in C v dd1 gnd1 isolated 5 v 0.1 f mclkin mdat v dd2 gnd2 non- isolated 5 v/3.3 v 0.1 f sinc 3 filter clock data gnd v dd sclk sdat cs isolation barrier clock frequency, 256 decimation ratio and 16-bit word settings, the output data rate is 39 khz (= 10 mhz/256). this filter can be implemented in an asic, an fpga or a dsp. some of the adc codes with corresponding input voltages are shown in table 10. microcontroller. instead of a digital filter implemented in software, the hcpl-0872 can be used together with the acpl-796j to form an isolated programmable two-chip a/d converter (see figure 17). clock acpl-796j 3-wire serial interface input current r shunt v in + v in C v dd1 gnd1 isolated 5 v 0.1 f mclkin mdat v dd2 gnd2 non- isolated 5 v 0.1 f hcpl-0872 mclk1 mdat1 gnd v dd sclk sdat cs isolation barrier serial configuration port. a second multiplexed input is available to allow measurements with a second isolated modulator without additional hardware. refer to the hcpl-0872 data sheet for details. notes: spi and qspi are trademarks of motorola corp. microwire is a trademark of national semiconductor inc.
13 application information digital current sensing circuit figure 18 shows a typical application circuit for motor control phase current sensing. by choosing the appropriate shunt resistance, any range of current can be monitored, from less than 1 a to more than 100 a. acpl-796j floating positive supply r sense v in + v in C v dd1 gnd1 mclkin mdat v dd2 gnd2 non- isolated 5 v/3.3 v c3 0.1 f isolation barrier gate drive circuit hv+ hvC c1 0.1 f d1 5.1 v c2 10 nf motor r2 39 r1 +C figure 18. typical application circuit for motor phase current sensing. power supplies and bypassing as shown in figure 18, a floating power supply (which in many applications could be the same supply that is used to drive the high-side power transistor) is regulated to 5 v using a simple zener diode (d1); the value of resistor r1 should be chosen to supply sufficient current from the existing floating supply. the voltage from the current sensing resistor or shunt (r sense ) is applied to the input of the acpl-796j through an rc anti-aliasing filter (r2 and c2). and finally, a clock is connected to the acpl-796j and data are connected to the digital filter. although the appli- cation circuit is relatively simple, a few recommendations should be followed to ensure optimal performance. the power supply for the isolated modulator is most often obtained from the same supply used to power the power transistor gate drive circuit. if a dedicated supply is required, in many cases it is possible to add an addi- tional winding on an existing transformer. otherwise, some sort of simple isolated supply can be used, such as a line powered transformer or a high-frequency dc-dc converter. an inexpensive 78l05 three terminal regulator can also be used to reduce the floating supply voltage to 5 v. to help attenuate high-frequency power supply noise or ripple, a resistor or inductor can be used in series with the input of the regulator to form a low-pass filter with the regulators input bypass capacitor. as shown in figure 18, 0.1 f bypass capacitors (c1 and c3) should be located as close as possible to the input and output power-supply pins of the isolated modulator. the bypass capacitors are required because of the high-speed digital nature of the signals inside the isolated modulator. a 10 nf bypass capacitor (c2) is also recommended at the input due to the switched-capacitor nature of the input circuit. the input bypass capacitor also forms part of the anti-aliasing filter, which is recommended to prevent high frequency noise from aliasing down to lower frequencies and interfering with the input signal. pc board layout the design of the printed circuit board (pcb) should follow good layout practices, such as keeping bypass capacitors close to the supply pins, keeping output signals away from input signals, the use of ground and power planes, etc. in addition, the layout of the pcb can also affect the isolation transient immunity (cmr) of the isolated modulator, due primarily to stray capacitive coupling between the input and the output circuits. to obtain optimal cmr perfor- mance, the layout of the pc board should minimize any stray coupling by maintaining the maximum possible distance between the input and output sides of the circuit and ensuring that any ground or power plane on the pc board does not pass directly below or extend much wider than the body of the isolated modulator.
14 shunt r esistors the current-sensing shunt resistor should have low re- sistance (to minimize power dissipation), low inductance (to minimize di/dt induced voltage spikes which could adversely affect operation), and reasonable tolerance (to maintain overall circuit accuracy). choosing a particu- lar value for the shunt is usually a compromise between minimizing power dissipation and maximizing accuracy. smaller shunt resistances decrease power dissipation, while larger shunt resistances can improve circuit accuracy by utilizing the full input range of the isolated modulator. the first step in selecting a shunt is determining how much current the shunt will be sensing. the graph in figure 19 shows the rms current in each phase of a three- phase induction motor as a function of average motor output power (in horsepower, hp) and motor drive supply voltage. the maximum value of the shunt is determined by the current being measured and the maximum rec- ommended input voltage of the isolated modulator. the maximum shunt resistance can be calculated by taking the maximum recommended input voltage and dividing by the peak current that the shunt should see during normal operation. for example, if a motor will have a maximum rms current of 10 a and can experience up to 50% overloads during normal operation, then the peak current is 21.1 a (= 10 1.414 1.5). assuming a maximum input voltage of 200 mv, the maximum value of shunt resistance in this case would be about 10 m . figure 19. m otor o utput horsepower vs. m otor phase current and supply. 15 5 40 15 20 25 30 25 motor phase current - a ( rms ) 10 30 motor output power - horsepower 535 0 0 440 380 220 120 10 20 35 the maximum average power dissipation in the shunt can also be easily calculated by multiplying the shunt resistance times the square of the maximum rms current, which is about 1 w in the previous example. if the power dissipation in the shunt is too high, the resis- tance of the shunt can be decreased below the maximum value to decrease power dissipation. the minimum value of the shunt is limited by precision and accuracy require- ments of the design. as the shunt value is reduced, the output voltage across the shunt is also reduced, which means that the offset and noise, which are fixed, become a larger percentage of the signal amplitude. the selected value of the shunt will fall somewhere between the minimum and maximum values, depending on the par- ticular requirements of a specific design. when sensing currents large enough to cause signifi- cant heating of the shunt, the temperature coefficient (tempco) of the shunt can introduce nonlinearity due to the signal dependent temperature rise of the shunt. the effect increases as the shunt-to-ambient thermal resis- tance increases. this effect can be minimized either by reducing the thermal resistance of the shunt or by using a shunt with a lower tempco. lowering the thermal resis- tance can be accomplished by repositioning the shunt on the pc board, by using larger pc board traces to carry away more heat, or by using a heat sink. for a two-terminal shunt, as the value of shunt resistance decreases, the resistance of the leads becomes a signifi- cant percentage of the total shunt resistance. this has two primary effects on shunt accuracy. first, the effective resis- tance of the shunt can become dependent on factors such as how long the leads are, how they are bent, how far they are inserted into the board, and how far solder wicks up the lead during assembly (these issues will be discussed in more detail shortly). second, the leads are typically made from a material such as copper, which has a much higher tempco than the material from which the resistive element itself is made, resulting in a higher tempco for the shunt overall. both of these effects are eliminated when a four-terminal shunt is used. a four-terminal shunt has two additional terminals that are kelvin-connected directly across the resistive element itself; these two terminals are used to monitor the voltage across the resistive element while the other two terminals are used to carry the load current. because of the kelvin connection, any voltage drops across the leads carrying the load current should have no impact on the measured voltage. several four-terminal shunts from isotek (isabellenhtte) suitable for sensing currents in motor drives up to 71 arms (71 hp or 53 kw) are shown in table 11; the maximum current and motor power range for each of the pbv series shunts are indicated. for shunt resistances from 50 m down to 10 m , the maximum current is limited by the input voltage range of the isolated modulator. for the 5 m and 2 m shunts, a heat sink may be required due to the increased power dissipation at higher currents.
15 table 11. isotek (isabellenhtte) four-terminal shunt summary. shunt r esistor part n umber shunt r esistance tol. m aximum rm s current m otor power r ange 1 2 0 v ac - 440 v ac m % a hp kw pbv-r050-0.5 50 0.5 3 0.8 - 3 0.6 - 2 pbv-r020-0.5 20 0.5 7 2 - 7 0.6 - 2 pbv-r010-0.5 10 0.5 14 4 - 14 3 - 10 pbv-r005-0.5 5 0.5 25 [28] 7 - 25 [8 - 28] 5 - 19 [6 - 21] pbv-r002-0.5 2 0.5 39 [71] 11 - 39 [19 - 71] 8 - 29 [14 - 53] note: values in brackets are with a heatsink for the shunt. when laying out a pc board for the shunts, a couple of points should be kept in mind. the kelvin connections to the shunt should be brought together under the body of the shunt and then run very close to each other to the input of the isolated modulator; this minimizes the loop area of the connection and reduces the possibility of stray magnetic fields from interfering with the measured signal. if the shunt is not located on the same pc board as the isolated modulator circuit, a tightly twisted pair of wires can accomplish the same thing. also, multiple layers of the pc board can be used to increase current carrying capacity. numerous plated-through vias should surround each non-kelvin terminal of the shunt to help distribute the current between the layers of the pc board. the pc board should use 2 or 4 oz. copper for the layers, resulting in a current carrying capacity in excess of 20 a. making the current carrying traces on the pc board fairly large can also improve the shunts power dissipa- tion capability by acting as a heat sink. liberal use of vias where the load current enters and exits the pc board is also recommended. shunt connections the recommended method for connecting the isolated modulator to the shunt resistor is shown in figure 18. v in + of the acpl-796j is connected to the positive terminal of the shunt resistor, while v in C is shorted to gnd1, with the power-supply return path functioning as the sense line to the negative terminal of the current shunt. this allows a single pair of wires or pc board traces to connect the isolated modulator circuit to the shunt resistor. by refer- encing the input circuit to the negative side of the sense resistor, any load current induced noise transients on the shunt are seen as a common-mode signal and will not interfere with the current-sense signal. this is important because the large load currents flowing through the motor drive, along with the parasitic inductances inherent in the wiring of the circuit, can generate both noise spikes and offsets that are relatively large compared to the small voltages that are being measured across the current shunt. if the same power supply is used both for the gate drive circuit and for the current sensing circuit, it is very important that the connection from gnd1 of the isolated modulator to the sense resistor be the only return path for supply current to the gate drive power supply in order to eliminate potential ground loop problems. the only direct connection between the isolated modulator circuit and the gate drive circuit should be the positive power supply line. in some applications, however, supply currents flowing through the power-supply return path may cause offset or noise problems. in this case, better performance may be obtained by connecting v in + and v in C directly across the shunt resistor with two conductors, and connecting gnd1 to the shunt resistor with a third conductor for the power-supply return path, as shown in figure 20. when connected this way, both input pins should be bypassed. to minimize electromagnetic interference of the sense signal, all of the conductors (whether two or three are used) connecting the isolated modulator to the sense resistor should be either twisted pair wire or closely spaced traces on a pc board. the 39 resistor in series with the input lead (r2) forms a low pass anti-aliasing filter with the 10 nf input bypass capacitor (c2) with a 400 khz bandwidth. the resistor performs another important function as well; it dampens any ringing which might be present in the circuit formed by the shunt, the input bypass capacitor, and the inductance of wires or traces connecting the two. undamped ringing of the input circuit near the input sampling frequency can alias into the baseband producing what might appear to be noise at the output of the device.
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2011 avago technologies. all rights reserved. av02-1670en - march 25, 2011 v oltage sensing the acpl-796j can also be used to isolate signals with am- plitudes larger than its recommended input range with the use of a resistive voltage divider at its input. the only restrictions are that the impedance of the divider be rela- tively small (less than 1 k ) so that the input resistance (33 k ) and input bias current (0.5 a) do not affect the accuracy of the measurement. an input bypass capacitor is still required, although the 39 series damping resistor figure 2 0. schematic for three conductor shunt connection. acpl - 796j f loa ti ng pos iti ve supply r sense v i n + v i n C v dd 1 gnd 1 mclk i n mda t v dd2 gnd2 non - i sola t ed 5 v/3.3 v i sola ti on barr i er ga t e dr i ve c i rcu it h v + h vC c 1 0. 1 f d 1 5. 1 v c2a 1 0 n f mo t or r2a 39 r 1 c2b 1 0 n f r2b 39 + C 0. 1 f + C c3 is not (the resistance of the voltage divider provides the same function). the low-pass filter formed by the divider resistance and the input bypass capacitor may limit the achievable bandwidth. to obtain higher bandwidth, the input bypass capacitor (c2) can be reduced, but it should not be reduced much below 1000 pf to maintain adequate input bypassing of the isolated modulator.

▲Up To Search▲

Price & Availability of ACPL-796J-560E

	To Download ACPL-796J-560E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .